A conventional serializer-to-deserializer (“SERDES”) receiver has an analog architecture used to perform a combination of continuous time analog equalization and analog decision feedback equalization. However, more recently, an analog-to-digital converter (“ADC”) has been used to digitize a received analog signal and then perform digital equalization and digital data recovery.
Because of the high speeds used by some SERDES, an ADC used for this purpose is conventionally a flash ADC, also known as a direct-conversion ADC or a parallel ADC. A flash ADC conventionally includes a bank of comparators for sampling an input signal in parallel. Every comparator in such bank is used for each sampling cycle, where each comparator has an associated voltage range. Direct conversion via a flash ADC is capable of gigahertz sampling rates, and so flash ADCs are useful in high bandwidth or wideband applications, where resolution may be limited to 8-bits or so. However, such speed comes at a price of a high input capacitance and high power dissipation
Hence, it would be useful to provide a flash ADC that overcomes or mitigates one or more of these limitations.